Conventionally, an insulated gate bipolar transistor (IGBT) has been experimentally fabricated that uses a silicon carbide (SiC) semiconductor as the semiconductor material (hereinafter, referred to as “SiC-IGBT”) as a semiconductor device including MOS gate (insulated gate formed by a metal oxide film semiconductor) structures of a planar gate type. The structure of a conventional planar gate SiC-IGBT will be described below. FIGS. 14 and 15 are cross-sectional views of the structure of a conventional planar gate SiC-IGBT. FIG. 14 depicts a p-channel IGBT and FIG. 15 depicts an n-channel IGBT.
In the p-channel IGBT depicted in FIG. 14, on one surface side of a p−-type drift layer 101, components are disposed such as a MOS gate structure including an n-type base region 102, a p+-type emitter region 103, a gate insulation film 104, and a gate electrode 105, and an emitter electrode 106. On the other surface side of the p−-type drift layer 101, a p-type buffer layer 107, an n+-type collector layer 108, and a collector electrode 109 are disposed. The n-channel IGBT depicted in FIG. 15 has a structure formed by inverting the conductivity types of the p-channel IGBT depicted in FIG. 14. Reference numerals “111” to “119” respectively denote an n−-type drift layer, a p-type base region, an p+-type emitter region, a gate insulation film, a gate electrode, an emitter electrode, an n-type buffer layer, a p+-type collector layer, and a collector electrode.
Operation of the IGBT will be described taking an example of the n-channel IGBT. When positive voltage is applied to the gate electrode 115, an inversion layer of the p-type base region 112 is excited in a surface layer of a region immediately under the gate electrode 115. Through this inversion layer, electrons are injected from the n+-type emitter region 113 into the p-type base region 112 of the surface layer of the n−-type drift layer 111. The electrons injected into the p-type base region 112 pass through the n−-type drift layer 111 and reach the p+-type collector layer 118. Holes (positive holes) are injected from the p+-type collector layer 118 toward the n−-type drift layer 111. Thereby, the IGBT transitions to the “ON” state. In the “ON” state, the electrons and the holes accumulate inside the n−-type drift layer 111 such that the charge neutralization condition is satisfied, and the carrier concentration of the n−-type drift layer 111 is increased.
The electric conductivity in the n−-type drift layer 111 is increased (conductivity modulation) and the “ON” voltage when a predetermined current flows is reduced. For the holes to be injected from the p+-type collector layer 118 toward the n−-type drift layer 111, a forward voltage substantially equal to a built-in voltage needs to be applied to a p-n junction between the p+-type collector layer 118 and the n−-type drift layer 111. For a bipolar device using the silicon carbide semiconductor as the semiconductor material, because the built-in voltage is high, the current rise voltage is high and the rate of the build-in voltage accounting for in the “ON” voltage is high in the “ON” state. A unipolar device having no built-in voltage is, therefore, advantageous in a breakdown voltage class including breakdown voltages up to several kV. On the other hand, the bipolar device using a silicon carbide semiconductor is suitable for a device in a breakdown voltage class including voltages greater than or equal to 10 kV.
To reduce the electrical resistance (the “ON” voltage) by accumulating the carriers (electrons and holes) in the n−-type drift layer 111, it is necessary to efficiently inject the electrons from the emitter side to the n−-type drift layer 111 and efficiently inject the holes from the collector side to the n−-type drift layer 111. To efficiently inject the holes from the collector side, the impurity concentration of the p+-type collector layer 118 merely has to be increased. On the other hand, to efficiently inject the electrons on the emitter side, the carriers (the electrons and holes) merely have to be confined to the n−-type drift layer 111 as many as possible, that is, the effect of electron injection enhancement (injection enhanced (IE)) merely has to be enhanced. The IE effect is a technique that is widely used to improve the property of the IGBT using silicon (Si) as the semiconductor material (hereinafter, referred to as “Si-IGBT”).
The following two structures are already in practical use as front face element structures each having the IE effect. FIG. 16 is an explanatory diagram of a structure of a conventional trench gate Si-IGBT. In FIG. 16, the carrier distribution in the n−-type drift layer 111 is depicted on the right, and the flows of the carriers in the “ON” state are depicted using arrows in a cross-sectional view on the left. FIG. 17 is a perspective diagram of the structure of another example of a conventional trench gate Si-IGBT. The first structure is an injection enhanced gat transistor (IEGT) structure that accumulates the holes in the n−-type drift layer 111 in a vicinity of a bottom portion of the trench in the “ON” state by reducing the width of a mesa region (hereinafter, referred to as “mesa width”) between adjacent trenches (trenches each having the gate electrode 115 embedded therein) (FIG. 16). The second structure is a carrier-stored trench-gate bipolar transistor (CSTBT) structure formed by inserting an n-type carrier accumulation (carrier-stored (CS)) layer 120 between the n−-type drift layer 111 and the p-type base region 112 in the mesa region between the adjacent trenches (FIG. 17).
For a trench gate Si-IGBT, the IE effect can be enhanced by setting the front face element structure to be a structure having a narrow mesa width or a structure having a CS layer disposed therein. On the other hand, for a planar gate Si-IGBT, the IE effect is difficult to enhance and any improvement of attributes is, therefore, limited. For a SiC-IGBT, it is also effective to enhance the IE effect to improve attributes. To realize an attribute exceeding that of the planar gate SiC-IGBT, the trench gate SiC-IGBT is employed and the front face element structure is set to be a structure having a narrow mesa width or a structure having the CS layer disposed therein, whereby improvement of the property can be expected. For example, when a structure having a narrow mesa width is applied, a voltage drop is generated by concentrating the hole current in the mesa region and thereby, the injection is enhanced of the electrons from the electron accumulation layer (the inversion layer) formed in the trench side wall to the drift layer.
According to a device that has been proposed as a semiconductor device having the IE effect, an n-type layer having an impurity concentration higher than that of the n−-type drift layer is disposed between the n−-type drift layer and the p-type base layer, whereby the carrier distribution in the n−-type drift layer substantially becomes like the carrier distribution in a diode, and the “ON” voltage is reduced maintaining the current value capable of being turned off to be high (see, for example, Japanese Laid-Open Patent Publication No. H08-316479).
According to a another proposed device, an n-type layer having a higher concentration than that of an n−-type layer is disposed between the n−-type layer and the p-type layer in an IGBT including at least a “p+n−pn+” structure from the collector side toward the emitter side (see, for example, Japanese Laid-Open Patent Publication No. H10-178174).
The following device has also been proposed as yet another device. A drift layer of a second conductivity type is disposed on a substrate of a first conductivity type. A current suppression layer is disposed on the drift layer. The current suppression layer is of a second conductivity type and has a doping concentration that is higher than the doping concentration of the drift layer. A well region of the first conductivity type is present in the current suppression layer. The well region has a junction depth that is smaller than the thickness of the current suppression layer, and the current suppression layer laterally extends under the well region. An emitter region of the second conductivity type is present in the well region (see, for example, Japanese Laid-Open Patent Publication No. 2008-211178).
According to yet another proposed device, an n-type impurity diffusion region (an embedded diffusion layer) having a relatively high concentration is disposed in a vicinity of a region for an n−-type drift layer to constitute a p-n junction with a p-type body region in a structure of a MOS transistor portion (see, for example, Published Japanese-Translation of PCT Application, Publication No. 2009/122486 (paragraph 0079 and FIG. 39)).
The following device has also been proposed as yet another device. An n+-type semiconductor layer (nCELb) is disposed on the surface of an n−-type drift layer. The impurity concentration of nCELb is higher than the impurity concentration of the n−-type drift layer. An n-type semiconductor layer (nCELu) is disposed on the surface of nCELb. The impurity concentration of nCELu is higher than the impurity concentration of the n−-type drift layer and is lower than the impurity concentration of nCELb. A p-type body region is selectively disposed in the surface layer of nCELu (see, for example, Japanese Laid-Open Patent Publication No. 2013-089700).
A device has also been proposed as yet another device that includes an n-type drift layer stacked on one surface of a p-type silicon carbide semiconductor substrate having a high impurity concentration, an n-type carrier storage layer having an impurity concentration higher than that of the drift layer and disposed inside the drift layer on the surface side to divide the drift layer into two layers of an upper and a lower layer, a p-type base region disposed in the surface-side drift layer of the two divided drift layers, an n-type emitter region disposed in the surface layer of the p-type base region, and a gate electrode disposed through a gate insulation film on the surface of the p-type base region and on the surface of the surface-side drift layer whose side face is adjacent to the p-type base region and whose main face is in contact with the carrier storage layer (see, for example, Japanese Laid-Open Patent Publication No. 2013-149798).
According to another proposed device, an n-type charge accumulation layer and a p-type body layer are sequentially disposed on an n−-type Si substrate, and a trench gate is disposed through a gate insulation film in a trench that penetrates the p-type body layer (see, for example, Japanese Laid-Open Patent Publication No. 2013-187440 (paragraph 0013 and FIG. 1)).
To inject the carriers into the n−-type drift layer, however, a high forward bias needs to be applied to the p-n junction between the p-type base region and the n−-type drift layer because the built-in voltage of the silicon carbide semiconductor is high. With the SiC-IGBT applied with the front face element structure having a narrow mesa width (the width of the mesa region between adjacent trenches), when the voltage drop caused by the hole current in the mesa region is lower than the built-in voltage of the silicon carbide semiconductor, a problem arises in that the electron injection enhancement (IE) effect is not sufficiently achieved from the emitter side to the n−-type drift layer. To enhance the IE effect in the SiC-IGBT, the mesa width needs to be reduced to a length smaller than the Si-IGBT and the trench depth needs to be increased, however, problems arise in that deep etching of the trench is difficult and the patterning to form the front face element structure having a narrow mesa width is also difficult.
When the front face element structure of the trench gate type is employed, a high electric field is applied to the bottom portion of the trench in a “normally off” state of the device and a problem arises in that the gate insulation film that is formed along the inner wall of the trench is degraded. Although the silicon carbide semiconductor has an advantage in that the critical electric field strength is high at which the avalanche breakdown occurs, however, the electric field applied to the gate insulation film is also increased and a problem, therefore, arises in that the long term reliability of the gate insulation film drops.